This invention pertains to computer video graphics systems and, more particularly, to a video graphics system in which processor access to the video memory is dependent upon the current fill level of a FIFO refresh buffer and the current mode of operation.
To display video data on a raster scan display device, such as a cathode ray tube (CRT) display, a typical video system includes a dedicated video memory for storing a full screen of video data. The video data to be displayed is transferred from the computer's central processor to the video memory. A CRT controller (CRTC) generates the appropriate horizontal and vertical sync pulses and associated timing signals and, at the appropriate time, a bit, byte or block of video data is read from the video memory, processed, and displayed on the screen. Unless dual ported video memory (VRAM) is used, the central processor can not access the video memory at the same time that the bit, byte or block of data is read from the video memory to "refresh" the screen. Consequently, a video memory read operation for purposes of screen refresh usually has priority over a central processor write operation to the video memory. If this were not the case, display data would momentarily disappear from the screen during periods of processor video memory access. Therefore, processor access to the video memory is usually limited to periods of horizontal and vertical blanking.
As the resolution of video systems increases, both in terms of pixels per screen and colors per pixel, the total number of bits or bytes per screen increases dramatically, along with the time required for the processor to re-write one screen of data into the video memory. Consequently, if processor access to the video memory is limited only to periods of horizontal and vertical blanking, eventually a point is reached at which the processor can not re-write the video memory fast enough to keep up with images that are constantly changing. One way to help overcome this problem is to buffer the refresh output of the video memory with, for example, a first in, first out buffer (FIFO). With a buffer at the refresh output of the video memory, a block of video data can be rapidly copied from the video memory to the buffer. Data stored in the buffer is then used to refresh the screen, however, until the buffer is emptied to a predetermined level, the processor can write new video data into the video memory, even during non-blanking periods.
There are a number of video or "graphics" standards available today. For example, a low resolution standard or "mode" may display only 320 by 200 pixels, with each pixel being one of four colors. In a high resolution mode, 1024 by 768 pixels may be displayed with each pixel being one of 256 colors. The predetermined level to which the buffer must be emptied before central processor access to the video memory is inhibited is, however, dependent upon the mode of operation. For high speed, high resolution modes, the buffer will be emptied rapidly and, therefore, the fill level of the buffer must be relatively high to permit central processor access to the video memory. On the other hand, for low speed, low resolution modes the buffer will be emptied more slowly and, consequently, the fill level at which processor access to the video memory is denied is much lower. Thus, in a video system having a plurality of programmable operating modes and a refresh buffer, it is desirable to allow processor access to the video memory at a number of different buffer fill levels depending on the mode of operation. Although the fill level at which processor access is denied can be fixed for all modes of operation, a variable level provides increased performance. Accordingly, the invention described below adjusts the minimum fill level for processor video memory access as a function of the current operating mode of the video system.